1. Field of the Invention
This invention relates to a flash EPROM memory array architecture, and more particularly the invention relates to a memory array which can be operated at a low voltage power supply with minimal gate and drain disturbance during operation.
2. Field of Prior Art
FIG. 1A is a section view of a prior art flash EPROM device in which an N+ source 10 and N+ drain 12 are formed in the surface of a P- semiconductor substrate 14. A floating gate 16 is provided between a control gate 18 and the surface of the substrate 14, and between the source 10 and the drain 12. The device is programmed to a high threshold voltage state by applying high voltage (about 6.5 to 7 volts) on the drain and high voltage (about 12-13 volts) on the control gate so that hot electrons are injected into the floating gate near the edge of the drain junction. The programming efficiency of the device in FIG. 1A strongly depends on the channel length, channel doping concentration, doping profile of the drain junction, and especially, the drain voltage since the programming occurs at the drain side of the floating gate transistors, referred to herein as drain side programming.
The typical drain voltage for drain side programming is about 6.5 to 7 volts and the typical programming current is in the range of 500 uA to 1 mA per bit. The 6.5 to 7 volts of programming voltage usually is obtained by reducing it from a separate 12 volts power supply. Thus, the memory circuit operation needs two power supplies: a 5 volts power supply and a 12 volts power supply. To use a single low voltage power supply (e.g. 5 volts) operation, either a very large charge pump is needed to supply the large programming current which is in the range of several milliamperes for one byte (8 bits) of programming, or a heavily doped channel concentration with specially designed drain junction is needed so that enough programming speed is provided and at the same time soft-write during read operation (read disturb) is avoided. Both of the approaches are difficult to achieve.
Erase of the device in FIG. 1A is achieved either by applying a high voltage (about 12 to 13 volts) on the source 10 and ground to the control gate 18, or by applying 5 volts on the source 10 and a negative voltage (about -11 volts) on the control gate 18. One big problem of this device during erase operation is that is cannot be over-erased. If the device is over-erased to become a depletion transistor, it will conduct leakage current during the read operation of the other memory cells, for the same accessed bit line.
Read operation of the device is achieved by applying a low voltage (about 1 volt) on the drain 12 and 5 volts on the control gate 18. The low threshold voltage cell (non-programmed cell) will conduct current and is read as a `1` state, and the high threshold voltage cell (programmed cell) will not conduct current and will be read as a `0` state.
A typical memory array architecture using the device in FIG. 1A is shown in FIG. 1B. In this array architecture, the control gates extend in one direction to form word lines and the drains extend in another direction to form bit lines with the bit lines perpendicular to the word lines. Usually, 8 or 16 bit lines share one common source line. The access of a certain memory cell is achieved by selecting one bit line and one word line, and the cell at the cross point of the selected bit line and word line is selected. During the programming of the selected cell A, selected bit line B1 is at 6.5 to 7 volts and selected word line W1 is at 12 volts and all the other unselected lines are at 0 volt. In this situation, cell A will be programmed to high threshold voltage. However, the memory cell B which is connected to the selected bit line but on an unselected word line is stressed at high drain voltage with gate grounded as shown in FIG. 1C. This condition is usually called drain disturb. For the case of 100 .ANG. first gate oxide thickness and 15% of drain coupling, the electric field between the drain and the floating gate is about 5.5 to 6 MV/cm under the drain disturb condition as shown in FIG. 1C.
The drain disturb on cell B occurs not only during the programming of the cell A but also during the programming of the rest of the cells connected to the same bit line B1. If cell B has been programmed to high threshold voltage prior to cell A and the rest of the cells connected to bit line B1, this high drain voltage may discharge the floating gate charge of the cell B by the electric field between the floating gate and the drain. As described above, the programming of the memory cell in this array architecture is achieved by drain side hot electron injection. The drain voltage during programming cannot be too low otherwise the programming speed will be too slow. But, the drain voltage during programming cannot be too high because of the drain disturb condition that limits the drain voltage during programming for this array architecture. The limitation on the drain voltage necessitates very high channel doping for optimizing the programming performance. However, high channel doping creates other disturbance problems such as read disturb, and also reduces the bit line junction breakdown voltage which makes the erase junction difficult to optimize. Thus, the drain disturb during programming imposes a limitation on the process window and scaling of the array.
Besides the drain disturb, this array architecture also has gate disturb problems during programming. For example, during programming of the selected cell A, the memory cell on the unselected bit line and on the selected word line such as cell C is under the stress condition as shown in FIG. 1D, which is called gate disturb. The 12 volts on the control gate and 0 volt on both drain and source will result in about 6 MV/cm of electric field between the floating gate and the substrate surface if 50% of control gate coupling is used and may cause electron tunneling from the substrate into the floating gate through the thin dielectric (typically 100 .ANG.) during the program operation of cell A and any other cell connected to word line W1. The gate disturb condition limits the maximum voltage that can be used on the control gate for programming such that the programming performance cannot be optimized by increasing the word line voltage. This also burdens the optimization of the programming performance. Both the drain disturb and the gate disturb conditions in this array architecture narrow the process window and reduce the design margin.
Assume the memory array as shown in FIG. 1B is separated into small blocks with several word lines as a memory block. During erase of the memory cell of the selected memory block such as cells A and C by employing the negative gate erase scheme, a -11 volts will be applied on the selected word line W1 and 5 volts will be applied on the common source line such that the charge on the floating gates of cells A and C can be discharged by the electric field between the floating gate and the source. However, the source of the unselected cells B and D will also have 5 volts on it since cell B and D share the same source with cells A and C. Considering the situation that cells A and C are programmed and erased for 10,000 cycles with typically erase time of 1 second for each erase cycle, the source of the cells B and D will be stressed by 5 volts for at least 10,000 seconds. Charge on the floating gate can be easily discharged by this stress condition. Usually this erase disturb is prevented by adding a pass transistor which can be selectively turned off to block the source voltage for the unselected cells. However, this adds some overhead on the chip size and complicates the circuit design.
Besides the disturb conditions during program and erase, the memory architecture as shown in FIG. 1B also suffers from the read disturb during read operation if the memory cell is not optimized. The read operation on cell A is achieved by applying a low voltage about 1 volt on the bit line B1 and 5 on the word line W1. The bit line voltage cannot be too high because the high bit line voltage on the drain of cell A and 5 volts gate voltage is under a programming condition, albeit slow programming. Since the channel doping is usually very high for optimizing the programming speed, channel doping also enhances the programming of the cell during a read condition. Thus, optimization of the channel doping and special designed drain junction are usually needed for this type of array architecture.
To summarize, all the above disturbance conditions are caused by the array architecture in which a word line is arranged to be perpendicular to both the drain and the source lines such that all the unselected cells will be stressed either by high control gate voltage or high drain/source voltage with all other terminals grounded. The common source architecture also creates disturbance during the erase operation and cannot prevent the disturbance during a read operation. All of these disturb conditions narrow the process window and make the optimization and scaling of the memory cell difficult.
FIG. 2A is a section view of a prior art memory device again having N+ source 20 and N+ drain 22 in a surface of P-substrate 24 with floating gate 26 between a control gate electrode 27 and the surface of the substrate 24, both of which overlap the source and a portion of the channel region. An addressing gate electrode 28 is formed on the control gate electrode, and extends to a portion of the channel region not covered by the floating gate and the control gate electrodes. Erase of the device in FIG. 2A is achieved by applying about 50 volts on the control gate to remove electrons from the floating gate through the dielectric between the floating gate and the control gate by Fowler-Nordheim tunneling. Due to the presence of the addressing gate, this device will not leak current even if the floating gate transistor is over-erased because the addressing gate can still turn off the device. The structure as shown in FIG. 2A effectively includes a floating gate transistor and an addressing gate transistor in series and is referred to a split gate structure.
Programming of this device is done by applying 25 volts on the control gate 27 and by applying 10 volts on both the drain 22 and the addressing gate 28. The high drain voltage is transferred by the addressing gate to the drain side of the floating gate transistor. The electrons moving through the channel cause an impact ionization near the drain side of the floating gate transistor due to a high electric field and thereby produce hot electrons with the high energy. Part of the hot electrons are injected into the floating gate 26 due to the high voltage coupling from the control gate 27 such that the device assumes a high threshold voltage state. Since the hot electrons are generated near the drain edge of the floating gate transistor, this programming mode is drain side injection and is the same as the device in FIG. 1A. Thus, the device in FIG. 2A still needs high drain voltage for programming and operating voltage is difficult to reduce.
The memory array architecture of the device in FIG. 2A is shown in FIG. 2B. In this array architecture, the control gate line runs perpendicular to the drain lines, and the addressing gate runs parallel with the control gate. This architecture does not have the drain disturb problem since its drain is not overlapped with the floating gate. However, the source region is self-aligned and overlapped by the floating gate. During programming of the cell 92-1, 10 volts are applied to the V.sub.D1 and V.sub.AG1 and 25 volts are applied to the V.sub.CG. Since all the control gates are at 25 volts and all the sources of the unselected cells 92-2 92-3, and 92-4 are at 0 volt, the unselected cells will have the gate disturb problem since the electrons may tunnel from the source into the floating gate through the thin dielectric between the floating gate and the source. One way to prevent this is to use thicker dielectric between the floating gate and the substrate. This necessitates that the memory cell be erased by electron tunneling through the dielectric on top of the floating gate instead of erased through the dielectric underneath the floating gate. However, erase through the dielectric on top of the floating gate usually is not uniform because the quality of the dielectric on the floating gate (oxide grown from polysilicon) is not as good as that grown from the substrate which is single crystalline silicon.
FIG. 3A is a section view of another prior art device which overcomes the over-erase problem by a split gate structure and can be programmed with lower drain voltage (5 volts instead of 6.5 to 7 volts) by using a different mechanism for hot electron injection. The advantage of using 5 volts on the drain for programming is the extra 12 volts power supply is not needed for this memory circuit operation and only a single low voltage (5 volts or 3 volts) power supply is needed. The device of FIG. 3A use a triple polysilicon structure including a floating gate 36, a control gate 38 and a select gate 39. The control gate 38 and the floating gate 36 overlap a portion of the channel region adjacent to the drain 32, and the select gate overlies another portion of the channel region adjacent to the source 30. Erase of the device is by applying a high voltage on the drain 32 and 0 volt on the control gate 38. Since it is a split gate structure, this device also does not have the over-erase concern.
Programming of the device is achieved by applying 5 volts on drain, 15 volts on the control gate, and about 1.5 to 2 volts on the select gate. The high control gate voltage heavily turns on the floating gate transistor and transfers the 5 volts drain voltage to the source side of the floating gate transistor. A high potential drop occurs at the substrate surface near the source edge of the floating gate transistor. The electrons in the channel are accelerated by this high potential drop and become hot electrons which can inject into the floating gate by high control gate voltage coupling. Since the hot electrons are generated and injected into the floating gate at the source side of the floating gate transistor, this programming mode has been referred as source side injection. It has been demonstrated that the source side injection can be 1000 times more efficient than the drain side injection. This is the reason why the device in FIG. 3A can be programmed with a lower drain voltage compared to the devices in FIG. 1A and FIG. 2A in which drain side injection is used. Moreover, since the select gate transistor is only slightly turned-on, the programming current is determined by the select transistor which can be less than 20 uA per bit. If further reduction of power supply is needed such as V.sub.cc =3 volts, the 5 volts drain voltage for programming is easily obtained by a charge pump circuit due to this small programming current. This indicates that it is possible to reduce the power supply voltage by implementing the source side injection method.
A typical memory array architecture of the device in FIG. 3A is shown in FIG. 3B. In this array architecture, the select gate 39 is formed by anisotropic etch of a third layer of polysilicon to form a sidewall gate structure adjacent to the control gate such that the orientation of the select gate line needs to be the same as the control gate. This requires that the select gate line be in parallel with the control gate line. Also, in this array architecture, the control gate and the select gate need to be perpendicular to the drain lines such that the access of a particular memory cell is achieved at the location where the bit line crosses with the control gate line and the select gate line. Since the selected bit line is perpendicular to the selected control gate line, it has the drain disturb and gate disturb concerns as described previously for the array architecture in FIG. 1B. Further, since the select gate 39 in FIG. 3A is formed by a sidewall etchback technique, it is difficult to apply silicide to form a silicide sidewall structure. Consequently, the RC delay along the select gate line will be large and degrade the speed performance of the memory circuit.
Thus, it is possible to use a single low voltage power supply for memory circuit operation if a source side injection mode is used. However, the array architecture as shown in prior art FIG. 3B will have both drain and gate disturb problems because the control gate line is arranged perpendicular to the drain lines, and the access of the memory cell is achieved at the location where the bit line crosses with both the control gate line and the select gate line. All these disturbances will reduce the endurance and degrade the reliability of the circuit. For major applications of flash memory such as for data storage, both the endurance and the reliability are critical. The only way to prevent these disturb conditions is to have a new array architecture such that the control gate line is in parallel with the drain lines and make the select gate line perpendicular to both the control gate and the bit line. The access of the memory cell is achieved at the location where the select gate line crosses with both the control gate line and the bit line. All the high voltage during program and erase is applied only to the control gate and the bit line, and the select gate line voltage is always kept as low as 0-2 volts.
It is therefore the main object of this invention to provide a new memory array architecture having the advantages of using source side injection for programming and with minimal disturbance during operation of the memory circuit.